This invention relates to a semiconductor device having a floating gate and control gate and a method for manufacturing the same.
A semiconductor device having a floating gate and control gate, for example, a MOS transistor can externally detect the level of a threshold voltage and thus be used as a memory element of a memory device.
The structure of a conventional MOS transistor with the above-mentioned double gates will be explained below with reference to FIGS. 1A and 1B. FIG. 1A is a cross sectional view as taken along a channel-length direction of a prior art semiconductor device and a cross sectional view as taken along a channel-width direction of FIG. 1A. In the arrangement shown in FIGS. 1A and 1B, n-type source and drain regions 12 and 13 are formed in the surface portions of a p-type semiconductor substrate 11, and a channel region 14 is formed between the source region and the drain region. An insulating layer (a gate insulating layer) is formed on the channel region 14. A floating gate 16 of a polysilicon is formed on the insulating layer 15. Then, an insulating layer 17 is formed on the floating gate 16 and a control gate 18 is formed on the insulating layer 17. A silicon dioxide (SiO.sub.2) layer 19 covers the whole surface of the above-mentioned MOS transistor. As shown in FIG. 1B, the MOS transistor area is isolated by a field insulating layer 20 from the other MOS transistor area.
In the above-mentioned MOS transistor the floating gate 16 is "electrically floated". A strong electric field is induced through the utilization of a coupling capacity present between the control gate 18 and the floating gate 16. As a result, a Fowler Noldheim type tunnel current flows through the layer 17 and charges are selectively injected into the floating gate 16, whereby data can be written into the MOS transistor. Upon applying a voltage between the source and the drain a channel current flows, producing hot electrons in the neighborhood of the drain 13. The hot electrons are injected into the floating gate 16, causing a rise in the threshold voltage of the MOS transistor whereby it is possible to write data in the MOS transistor, i.e., to permit a programming. Since the charges injected into the floating gate 16 continue to be held in the floating gate 16 unless a reprogramming is performed, the data once programmed is nonvolatilely held in the MOS transistor. The above-mentioned MOS transistor formed in a memory device is referred to, as required, as a memory cell.
In the memory device a situation must be avoided that charges are injected into a cell with respect to which a read/write operation is carried out or that the charges so injected flow out. As understood from the above, there is a risk that, with such a cell in that state, erroneous data will be read out of the memory device. For an enhanced integration density and microminiaturization of the memory device, insulating layers are made thinner and thinner and the temperature in the manufacturing process is made lower and lower. Therefore, there is a tendency that erroneous charges are injected or discharged more often in the memory cell. The floating gate 16 is usually formed of a polysilicon and isolated from the control gate 18 by a silicon dioxide (SiO.sub.2) layer 17 which is thermally formed on the surface of the floating gate 16. Due to the adoption of the lower oxidation temperature and formation of thinner and thinner SiO.sub.2 layers, an uneven surface is formed for the SiO.sub.2 layer, causing charges to be liable to concentrate locally and thus a leakage current to be liable to be produced across the gates 16 and 18.
In order to eliminate the above-mentioned drawbacks, the inventor has developed memory cells as shown in FIGS. 2A and 2B. The memory cell was disclosed in "1984 Symposium on VLSI Technology Digest of Technical Papers" p. 40 to 42, entitled "Poly-Oxide/Nitride/Oxide Structures for Highly Reliable EPROM Cells". This outline will be explained below with reference to FIGS. 2A (a cross sectional view as taken along a channel-length direction of a prior art semiconductor device) and 2B (a cross sectional view as taken in a channel-width direction of FIG. 2A). A composite insulating layer 24 is formed, as shown in FIGS. 2A and 2B, between a floating gate 16 and a control gate 18. The composite insulating layer 24 includes an SiO.sub.2 layer 21 formed by the thermal oxidation of the floating gate 16 of a polysilicon, a silicon nitride layer 22 formed on the layer 21 and an SiO.sub.2 layer 23 formed by the thermal oxidation of the surface of the layer 22. It has been found that this memory cell can reduce such leakage current to a greater extent than that in the memory cell of FIGS. 1A and 1B. However, it has been observed that, if the temperature of the manufacturing process is further reduced in the arrangement shown in FIGS. 2A and 2B, a larger leakage current is produced at an X point in FIG. 2A. Here, the X point shows the end portions of the composite layer 24 in the channel-length direction and the Y point shows the end portions of the composite layer 24 in the channel-width direction.
The enhanced integration density and the larger size of the silicon wafer are essential requirements under which it is possible to implement an inexpensive integrated circuit of an enhanced function. In order to satisfy these essential requirements it is unavoidable to adopt a low-temperature manufacturing process in which case the above-mentioned leakage current should be made as low as possible.